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Logic Design and Analysis using Verilog

Course Description

Expand your knowledge of gate level modeling, data flow modeling, behavior modeling, advanced modeling techniques, test benches, and logic synthesis. Learn the essentials of the Verilog hardware description language, syntax, and practical design scenarios. Participants learn fundamental and advanced usage of Verilog as a design capture and simulation development tool, and the use of the Programming Language Interface (PLI). The course will emphasize how Verilog is used in each step of the design automation process.

Prerequisite: Familiarity with digital logic design, electrical engineering, or equivalent experience.

Note: Textbook can be found in PDF format.

NOTE: needed for class, Zybo Z7-10 with SDSoC Voucher: Zynq-7000 ARM/FPGA SoC Development Board:

Choose the Zybo Z7-10 without SDSoC Voucher option.

For Academic Pricing on development board you will need to obtain a UCInetID - activate your UCInetID:

  • Be notified when this class becomes available!

  • Details
  • $745
  • Reg#: 00115
  • ID/Units: EECS X494.92  (3.00)
    ( Section 1 )
  • Quarter: WINTER 2022