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FPGA Design and Hardware Description Language

An elective course in the Certificate Program in Embedded Systems Engineering.

Course closed to new registrations: Call ( 949 ) 824-5414 for more information or sign up below to be notified when this course becomes available.×

Course Description

The goal of this course is to provide students material to gain a working understanding of FPGA architectures, design methodologies, FPGA development tools, prototyping hardware, FPGA synthesis, place and route, Static Timing Analysis, and FPGA image generation. This course’s approach involves learning new material via a series of lectures and then practicing that knowledge in labs, which build on top of one another. These labs are meant to provide practical design scenarios for students to apply what they have learned in a hands on setting. This course will focus exclusively on Verilog for RTL design and students will have the opportunity to create, modify, and debug designs through the labs. In lab, students will be asked to modify existing projects to accommodate more IP, add timing constraints so a design can pass timing, and physically validate models by programming your own FPGA board. The guided labs will provide enough context for the student to complete the final project. The final project has student’s create their own FPGA design, which needs to meet a set of given design specifications.

The objective of this class is to allow all students the opportunity to learn high-level FPGA design issues, the FPGA implementation flow and to debug FPGA hardware.

Recommended Prerequisites: Familiarity with electronics, digital logic and microprocessors or equivalent knowledge; and familiarity with a high level programming language such as C. NOTE: Students are required to purchase Development Board: Nexys 47-100T; SKU: 410-292 For academic pricing on development board you will need to obtain a UCInetID. To activate your UCInetID, visit and select the option for “Faculty, Staff and Students”. Enter your UCI DCE Reference ID# (format is X0123456), birth date, and the last 4 digits of your Social Security Number if available. Please contact the Office of Information Technology (OIT) at (949) 824-2222 with questions regarding your UCInetID.

NOTE: This course utilizes Zoom for weekly live online synchronous meetings. The sessions will be recorded and posted for students who are not able to attend, watching the recording is mandatory. The Zoom meeting link and password to join will be provided in your course. Students will need to have access to the internet, have speakers and a microphone to participate. The following student guide provides additional resources/information on how to use and access your courses Zoom sessions.

  • Be notified when this class becomes available!

  • Details
  • $745
  • July 05, 2021 to September 12, 2021
  • Delivery Mode: Online
  • Reg#: 00185
  • ID/Units: EECS X494.95  (3.00)
    ( Section 1 )
  • Quarter: SUMMER 2021


John C. Tramel, M.S., FPGA space-based applications design engineer at Northrop Grumman.He has 25 years of experience in teaching digital electronics at the University level.

Textbook Information

Textbooks for your course may be purchased from any vendor or bookseller of your choice.

Required Textbook(s):

Book - ISBN: 9780750689748
Clive Maxfeild, Elsevier Science

Meeting Schedule

EventDateDayStart TimeEnd TimeLocationRoom
START07/05/2021Monday------Online (Access Begins)---
OL-LEC07/05/2021Monday6:00 PM7:00 PMZoom---
OL-LEC07/12/2021Monday6:00 PM7:00 PMZoom---
OL-LEC07/19/2021Monday6:00 PM7:00 PMZoom---
OL-LEC07/26/2021Monday6:00 PM7:00 PMZoom---
OL-LEC08/02/2021Monday6:00 PM7:00 PMZoom---
OL-LEC08/09/2021Monday6:00 PM7:00 PMZoom---
OL-LEC08/16/2021Monday6:00 PM7:00 PMZoom---
OL-LEC08/23/2021Monday6:00 PM7:00 PMZoom---
OL-LEC08/30/2021Monday6:00 PM7:00 PMZoom---
OL-LEC09/06/2021Monday6:00 PM7:00 PMZoom---
END09/12/2021Sunday------Online (Access Ends)---