The goal of this course is to provide students material to gain a working understanding of FPGA architectures, design methodologies, FPGA development tools, prototyping hardware, FPGA synthesis, place and route, Static Timing Analysis, and FPGA image generation. This course’s approach involves learning new material via a series of lectures and then practicing that knowledge in labs, which build on top of one another. These labs are meant to provide practical design scenarios for students to apply what they have learned in a hands on setting. This course will focus exclusively on Verilog for RTL design and students will have the opportunity to create, modify, and debug designs through the labs. In lab, students will be asked to modify existing projects to accommodate more IP, add timing constraints so a design can pass timing, and physically validate models by programming your own FPGA board. The guided labs will provide enough context for the student to complete the final project. The final project has student’s create their own FPGA design, which needs to meet a set of given design specifications.
The objective of this class is to allow all students the opportunity to learn high-level FPGA design issues, the FPGA implementation flow and to debug FPGA hardware.
Recommended Prerequisites: Familiarity with electronics, digital logic and microprocessors or equivalent knowledge; and familiarity with a high level programming language such as C.
NOTE: Students are required to purchase Development Board: Nexys 47-100T; SKU: 410-292 https://store.digilentinc.com.
For academic pricing on development board you will need to obtain a UCInetID.
To activate your UCInetID, visit activate.uci.edu and select the option for “Faculty, Staff and Students”. Enter your UCI DCE Reference ID# (format is X0123456), birth date, and the last 4 digits of your Social Security Number if available. Please contact the Office of Information Technology (OIT) at (949) 824-2222 with questions regarding your UCInetID.