VHDL Design and Modeling of Digital Systems

Familiarize yourself with the analysis and synthesis of digital systems using VHDL to simulate and realize VLSI systems. Participants learn the fundamental concepts of VHDL and practical design techniques. The VHDL methodology and design flow for logic synthesis addresses design issues related to component modeling, data flow description in VHDL and behavioral description of hardware. An emphasis is placed on understanding the hardware description language, VHDL design techniques for logic synthesis, design criteria, and VHDL applications.