Logic Design and Analysis using Verilog

Expand your knowledge of gate level modeling, data flow modeling, behavior modeling, advanced modeling techniques, test benches, and logic synthesis. Learn the essentials of the Verilog hardware description language, syntax, and practical design scenarios. Participants learn fundamental and advanced usage of Verilog as a design capture and simulation development tool, and the use of the Programming Language Interface (PLI). The course will emphasize how Verilog is used in each step of the design automation process.